Prior art computer hard disk drives (HDDs) include a number of circuits for reading data and controlling the HDD. These circuits may include a PRML read channel (RDC), an ATA hard disk controller (HDC), a microcontroller (μc), and a motion control servo block. In such prior art devices, each of these devices may be provided as one or more separate and discrete integrated circuits or chips. Thus, the entire HDD electronics package may comprise a circuit board provided with such a set of chips, along with interconnection circuitry.
Such a design suffers from a number of faults. Most apparent of these is cost. The use of separate discrete components for drive control and read circuitry drives up costs by requiring an increased number of discrete devices, assembly, and interconnection circuitry. In addition, the use of multiple devices decreases overall production yield, as the probability of a faulty device or interconnection occurring increases with the number of such devices in a circuit. HDDs are cost-sensitive devices. In addition, the use of separate, discrete components increases overall power consumption in a hard disk drive or the like.
Ever more complex software drives the demand for more powerful computers with greater storage capacities—at prices equivalent to, or less than, previous generation models. Consumers generally will not replace existing computers unless newer models are faster, more powerful, have a greater storage capacity, and are cheaper (or as costly) as well.
In addition to cost, speed and reliability are also factors. Market pressure creates a need for faster hard drive access times, as computer programs become more complex and hard drives ever increase in capacity. Throughput speeds of over 200 Mb/s may be required, and speeds of over 250 Mb/s are desirable.
In the prior art, such read and controller circuitry was typically provided in separate circuits for a number of valid reasons. Chief among these was the desire to separate digital control signals for the hard drive from the analog read signals from the hard drive. Expertise in managing noisy analog data signals and digital control signals on the same integrated circuit device was simply not available. Although a HDD may be thought of as a digital device by most computer users, the data read from the read head (or written to the write head) of an HDD is in fact a rather noisy analog signal which must be converted to digital form in order to provide the proper data output. In addition, circuitry must generally be provided to supply error correction to such a data stream (due in part to the high noise level in HDD analog signals).
In addition, the use of discrete components for separate HDD functions allowed drive manufacturers to tailor a solution for a particular hard drive design based upon combinations of individual discrete components. An integrated circuit solution for one type of HDD may not be satisfactory for other manufacturers or models. Thus, different integrated circuits may have to be designed for different hard drive manufacturers.
In addition, prior art discrete HDD circuits may be manufactured using different integrated circuit technologies. For example, high performance partial response maximum likelihood (PRML) read channel circuits have been generally realized using BI-CMOS or N-MOS integrated circuit technology. See, for example, Welland, D. R., et. al., A Digital Read/Write Channel with EPR4 Detection, (ISSCC Digest of Technical Papers, pp. 276277, February, 1994), Mita, S. et. al., A 150 Mb/s PRML Chip for Magnetic Disk Drives, (ISSCC Digest of Technical Papers, pp.62–63, February, 1996), Fields, J., et. al., A 200 Mb/s EPRML Channel with Integrated Servo Demodulator for Magnetic Disks, (ISSCC Digest of Technical Papers, pp. 314–315, February, 1997), all of which are incorporated herein by reference. Such circuitry lends itself well to the large analog circuit portions typical of Prior Art read channel circuitry.
In contrast, other HDD system circuits, particularly digital control circuits, may be rendered in digital CMOS. Recent development of critical RDC blocks—such as an extended partial response, class 4 detector (EPR4), servo, finite impulse response (FIR) and interpolated timing recovery (ITR) in digital CMOS circuitry has enhanced volume manufacturability. See, for example, Tyson Tuttle, G., et. al., A 130 Mb/s Read/Write Channel with Digital Servo Detection, (SSCC Digest of Technical Papers, pp. 64–65, February, 1996), and Vishakhadadtta, G., et. al., A 245 Mb/s EPR4 Read/Write Channel with Digital Timing Recovery, (ISSCC Digest of Technical Papers, pp. 388–389, February, 1998), both of which are incorporated herein by reference.
In order to combine analog circuits such as the RDC with digital control circuits, a common integrated circuit technology may be needed in order to combine both analog and digital devices on one integrated circuit chip. As most Prior Art hard drive controller circuits utilize NMOS or Bi-CMOS circuitry, such designs may resist large scale integration. Simply stated, the resultant die size for an NMOS or Bi-CMOS integrated hard drive control may be too large.
Cirrus Logic, Inc., Mass Storage Division, Broomfield Colo., has been one of the few, if only, hard drive controller device manufacturers to utilize CMOS control circuits for both analog and digital circuitry in read channel controllers. The use of CMOS circuitry for both analog an digital devices is non-intuitive, as CMOS does not lend itself well (at least initially) to analog circuit design. However with the reduction from 0.8 micron technology to 0.35, 0.25 micron and smaller technologies, CMOS technology provides surprising advantages.
For example, in a read channel circuit, more analog components can be rendered as digital circuits. While such a design may initially appear to increase die size, as semiconductor technology shrinks to smaller resolutions (e.g., 0.25 micron), the resultant digital circuitry correspondingly shrinks. Analog circuitry, on the other hand, remains relatively static in size as integrated circuit technology shrinks. Thus, overall die size for a CMOS read channel circuit will shrink dramatically with decreases in semiconductor transistor size. Other types of technology (e.g., NMOS or Bi-CMOS) using largely analog circuits, do not show such a distinct shrinkage with decreases in transistor size.
Thus, CMOS read channels may be leveraged in system-level integration and, typically, benefit first from rapid process and lithography improvements. Moreover, the use of CMOS circuitry for an integrated hard drive controller remains a non-intuitive solution to the problem of further integrating hard drive circuitry.
In addition to the above-mentioned obstacles, such an integrated system-on-a-chip solution may be difficult to properly test, due to the inherent complexity of the device. Testing equipment and procedures for individual circuit components (RDC, ATA interface, processor, and the like), both for development and for production, are known in the prior art. However, an integrated HDD controller product may require an entirely new testing regime and equipment in order to properly test individual circuit functions. Moreover, given the level of integration, it might not be possible to properly and thoroughly test all circuits within such an integrated device due to the high level of integration.
In addition to testing difficulties, a large scale integrated device may be difficult to program and test. For example, a hard drive controller system may be programmed by an end user (e.g., hard drive manufacturer) with software or firmware which controls operation of the hard drive. Typically, such software development requires an iterative routine of programming and testing. Testing the hard drive controller may be achieved by running the software and monitoring selected pins of various devices in the hard drive controller.
For a Prior Art hard drive controller comprising a number of discrete circuit components, such development and testing provide little difficulty. However, when developing software for an integrated hard drive controller, a number of intermediate signal lines between components may not be “visible” at input or output pins of the device. Providing additional signal pins for such testing is expensive and difficult. Specialized chips may be made having such extra pins just for testing purposes. However, such chips are not representative of production devices and moreover incur additional cost in manufacturing such specialized devices.
Thus, what is needed is an inexpensive, integrated solution for a HDD read and control circuit which adequately protects digital signals from analog signal noise, using a common integrated circuit technology for all components, while still providing flexibility to be readily modified in design to work with a number of different HDD designs. In addition, a technique for testing individual elements within such a highly integrated circuit preferably using prior art equipment and methods would also be desirable, along with a technique for developing software for such a device.